The present invention relates generally to wafer level reliability testing of semiconductor devices and, more particularly, to accelerated MOSFET testing for negative bias temperature instability effects.
Negative bias temperature instability (NBTI) in a metal oxide semiconductor field effect transistor (MOSFET) is a serious problem to the long-term stability of the MOSFET, particularly p-type transistors and complementary metal oxide semiconductor (CMOS) devices having n+ polycrystalline silicon gates. NBTI results from charge buildup at the silicon-silicon oxide interface and is due to the influence of negative voltages on the gate electrode of MOS structures. As explained in an article titled xe2x80x9cImpact of Negative Bias Temperature Instability on the Lifetime of Single-Gate CMOS Structures with Ultrathin (4-6 nm) Gate Oxides,xe2x80x9d by Shigeo Ogawa et al., appearing in the Japanese Journal of Applied Physics, vol. 35, pt. 1, no. 2B, page 1484 (1996), the phenomenon arises after long-term stressing of the MOSFET at elevated temperatures and generally occurs even in low fields (6xc3x97106 volts/cm or less).
This instability is particularly pronounced in n+ polycrystalline silicon gate MOS structures, and was studied in the past extensively during the early stages of MOS transistor development. More recently, particularly with the development of high-speed MOS devices having gates with thin oxide layers, often less than 5 nm, there has developed a need for reliable testing techniques for such ultrathin oxides. One of the tests used to determine the life of devices having such thin oxide layers is a bias-temperature test (BT) and is based on NBTI of MOS structures. This test is performed at elevated temperature, although under constant voltage. The current state of the art achieves the necessary elevated temperature primarily by heating a wafer in an heating chuck. Such heating requires a long testing period to uniformly heat the wafers.
In U.S. Pat. No. 5,625,288 issued on Apr. 29, 1997 to Snyder et al., there is disclosed a different way to heat a test element. As shown in this reference, a polysilicon heater pad is placed near the test line. This configuration permits heating the test line without needing to raise the temperature of the full wafer.
Although the placement of heating pads adjacent the test element provides an obvious reduction in the time needed to raise the temperature of the test element, particularly when the test element is a thin line that is placed along the length of the heating pad, this technique still involves conductive heating of the wafer area containing the test element. When the test element is a MOSFET, the pads must heat an area sufficiently large to contain the full transistor structure so as to assure that the gate oxide layer has reached the desired temperature. Consequently, the process is again time consuming.
There is thus a need in the art of reliability testing of MOSFETs by NBTI techniques for the convenient and rapid increase in the temperature of the MOSFET gate oxide layer, preferably without having to heat the full wafer on which the transistor is built.
To meet this and other needs, and in view of its purposes, the present invention provides a test MOSFET structure. The structure comprises a MOSFET having a gate with a polysilicon layer. Two spaced electrical contact points are positioned on the polysilicon layer. This structure may be used in a test system for negative bias thermal instability testing of MOSFETs, the system comprising:
a) a test MOSFET device having a gate comprising a polysilicon layer with first and second gate contacts spaced from each other on the polysilicon layer; and
b) off-chip electronic circuitry for applying a heating current to the gate through the contacts, for applying a bias voltage to one of the gate contacts, and for measuring a shift in the applied bias voltage.
After forming the above structure, NBTI testing of a MOSFET is done. Such testing typically involves establishing a threshold bias voltage, heating and stressing the MOSFET under test, and measuring any shift on the established threshold voltage. According to the present invention, the testing process comprises forming a test MOSFET in a semiconductor substrate, the MOSFET having a gate comprising a polysilicon layer, two spaced gate electrical contacts on the polysilicon layer, and an oxide layer; and then applying a heating current through the gate contacts to produce a current flow in the polysilicon layer to raise its temperature thereby also raising the oxide layer temperature to a desired level. Typically, before applying the heating current, a threshold gate bias voltage is established and, following the step of applying the heating current, any shift in the threshold bias voltage is measured. Before measuring the threshold voltage shift and following application of the heating current, the additional step of stressing the MOSFET is performed by applying a stress voltage to one of the gate contacts.
In an alternate embodiment, the test MOSFET may comprise a combination of two adjacent MOSFETs each having a gate and, preferably, a common source. The gates are serially connected, each gate comprising a polysilicon layer, two spaced electrical contacts on the polysilicon layer, and an oxide layer. A first contact of the first MOSFET gate is connected to off-chip electronic circuitry for applying a heating current to the MOSFETs and a first contact of the second MOSFET gate is connected to the off-chip electronic circuit for applying a bias voltage to the second MOSFET.
One of the two MOSFETs is used to control the flow of current through the two gates through a feedback circuit and the other MOSFET is used for the NBTI testing. In this case, the testing process includes, in addition to the step of forming the two MOSFETs, applying a heating current to both gates by connecting the two MOSFET gates in series and connecting a contact of the first MOSFET gate and a contact of the second MOSFET gate to a current source.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.